Embodiments presented herein generally relate to integrated circuit (IC) memory devices, and more specifically, to dynamic random access memory (DRAM) with pseudo differential sensing.
Dynamic random access memory (DRAM) is a type of random access memory which utilizes separate capacitors to store each bit of data in a circuit based upon whether the capacitor is charged or discharged. A memory circuit is formed from an array of these DRAM cells can have a single bit line serving all of the cells in a given column of the array. Similarly, a single word line may serve all the cells in a given row. In this manner, data stored in one of the DRAM cells in the memory circuit can be read from the cell's capacitor through its respective bit line in response to the word line activating the cell.
DRAM cells and circuits may be produced using semiconductor lithography. Modern trends in DRAM production including scaling DRAMs to ever smaller lithography sizes. As sizes are reduced, it becomes more difficult to maintain reliability and performance as lithography error rates increase. What is needed is are techniques for mitigating error rates without having negative impacts on DRAM array timings, refresh rates, and system performance.